Skew Compensation by Changing Ground Parasitic For Traces

ABSTRACT

According to embodiments, small holes or openings may be cut on or through the ground plane(s) adjacent to a selected trace line, so that C and L will be changed accordingly. Then phase velocity will also be changed. As a result, the flying time from one location or point to a different location or point of the transmission line will also be changed. This concept applies to a single trace. Similarly, this concept may be applied to one trace of a differential pair of traces (e.g., so that the two parts of the differential signal transmitted at one point in time at a location on the pair arrive at the same time at another location of the pair).

This application is a continuation of pending U.S. patent applicationSer. No. 11/540,986 filed Sep. 28, 2006, entitled SKEW COMPENSATION BYCHANGING GROUND PARASITIC FOR TRACES.

FIELD

One or more embodiments relate generally to the field of signaltransmission lines or traces. More particularly, one or more embodimentsrelate to changing a signal phase velocity of a signal transmission on asignal line.

BACKGROUND

Signal lines, conductors, or traces are often used to transmit or sendsignals between devices or locations of an electronic device, such as aprinted circuit board (PCB), semiconductor chip package, or otherelectronic device or medium. In some cases the speed the signal travelsand/or time it takes to go from one location to another, such as over acertain distance, is important. Specifically, in cases of differentialsignal pairs of signal lines or signal traces, if a signal (e.g., acorresponding point in time of a differential signal) along one of thetraces arrives quicker than the signal on the other trace, thedifference in time may be defined as a “skew” (e.g., such as where thetwo traces have different length). Often, due to the layout of traces onan electronic device, rerouting of or complicated design of trace routesis necessary to reduce skew of differential signal pairs, and/or changesignal phase velocity for a single trace.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention are illustrated by way of example andnot by way of limitation in the figures of the accompanying drawings inwhich like references indicate similar elements. It should be noted thatreferences to “an” or “one” embodiment of the invention in thisdisclosure are not necessarily to the same embodiment, and they mean atleast one.

FIG. 1A is a top prospective view of an electronic device having a traceon a dielectric showing openings formed through a ground plane under thetrace.

FIG. 1B is a cross-section view of FIG. 1A through line A-A′.

FIG. 2A is a schematic cross-section view of a portion of an electronicdevice having a conductive layer on an insulator layer.

FIG. 2B shows the device of FIG. 2A after forming openings in theconductive layer.

FIG. 2C shows the device of FIG. 2B after forming an insulator materialon the conductive layer and through the openings.

FIG. 2D shows the device of FIG. 2C after forming a conductive materialon the insulator material.

FIG. 2E shows the device of FIG. 2D after removing portions of theconductor material to form a signal trace.

FIG. 2F shows a side perspective view of FIG. 2E.

FIG. 2G shows FIG. 2E after forming additional layers on the trace ofFIG. 2E.

FIG. 3 is a top perspective view of a differential pair of signal traceson a dielectric layer showing openings are formed through a ground planeof one trace.

FIG. 4A is a top perspective view of a pair of differential signals totransmit signals between two semiconductor chips.

FIG. 4B is an example of a schematic cross-section view through lineB-B′ of FIG. 4A.

DETAILED DESCRIPTION

The phase velocity of a signal transmitted in a signal line isdetermined by or proportional to the square root of the product of thecapacitance (C) and the inductance (L) of the transmission line per unitlength. For example, harmonic signal propagation in a transmission linemay be proportional to the product of C and L (e.g., identified by“(C·L)” or “(CL)”) of a line or trace a printed circuit board (PCB),semiconductor chip package, or other electronic device or medium. Morespecifically, the phase velocity of a signal may be equal to orproportional to (C·L)^(−1/2) as determined by the cross-sectionalgeometry and the material of: the transmission line: the dielectric orinsulator below, under, or adjacent to the transmission line; and/or oneor more ground planes below, under, or adjacent the dielectric orinsulator. It can be appreciated “the above” and “below” described isarbitrary, as the orientation of the line, dielectric, and plane may bereversed or otherwise oriented. Moreover, more than one dielectric layerand/or ground plane may effect the phase velocity, such as where a tracehas multiple ground planes (e.g., ground planes below, above, and/orbeside, etc. the trace). Also, in some cases the terms “transmissionline”, “line” and “trace” may be used interchangeably. Likewise, in somecases the terms “hole” and “opening” may be used interchangeably.Finally, the term “about” may be used to indicate an amount that iswithin 10, 5, 1, or 0.1 percent of a specified or target amount; orwithin an unsubstantial amount of the target amount for calculations orfunctions described herein.

According to embodiments, the harmonic signal propagation, signal speed,signal phase velocity, and/or “flying time” of a signal transmissionalong a signal line, or signal trace may be changed or adjusted bychanges in the capacitance (C) and/or inductance (L) of the line and/ortrace and ground. For example, the C (e.g., in Farads) and/or L (e.g.,Henries) of an electronic circuit between or including a trace and anadjacent or nearby ground (e.g., an electrically grounded conductor,plane, and/or surface) may be affected, changed, adjusted, or influencedby the shape, thickness, width, length, geometry, material and/orelectronic characteristics of the trace and ground, as well as that ofinsulator, dielectric, conductor, metal, alloy, semiconductor, siliconcontaining, and/or other materials or layers that are adjacent to,around, above, below, or otherwise have an effect on the C and/or L ofthe trace and ground.

Thus, according to embodiments, small holes or openings may be cut on orthrough the ground plane(s) adjacent to a selected trace line, so that Cand L will be changed accordingly. Then phase velocity will also bechanged. As a result, the flying time from one location or point to adifferent location or point of the transmission line will also bechanged. This concept applies to a single trace, such as a trace that isnot carrying or transmitting a differential signal. Similarly, thisconcept may be applied to one trace (e.g., the longer length traceand/or trace with a faster signal phase velocity) of a differential pairof traces (e.g., so that the two parts of the differential signaltransmitted at one point in time at a location on the pair arrive at thesame time at another location of the pair).

For instance, for differential signal pairs of traces D+ and D−, wheretheir length is not matched so that D+ and D− will have a skew atreceiver end. By cutting small holes on a ground plane adjacent to onetrace (D+ or D−), the phase velocity in D+compared to D− is adjusted, sothat even the D+ and D− trace lengths are not matched, the holes can becut for one of the traces to compensate or manipulate the skew bywithout the necessity of matching the length of D+ and D− or doing stackup changing. The same concept also applies to any other kind of signals,such as clock signals, that need timing consideration.

FIG. 1A is a top prospective view of an electronic device having a traceon a dielectric showing openings formed through a ground plane under thetrace. FIG. 1B is a cross-section view of FIG. 1A through line A-A′.Layer 108 may define a signal trace, differential signal trace of a pairof differential signal traces, signal line, or trace as known in theart. Trace 108 is formed on or touching insulator layer 106, which isformed on or touching conductive layer 104. Conductive layer 104 isformed on or touching insulator layer 102. Insulator layer 102 has topor upper surface 130 (e.g., disposed towards trace 108) and bottom orlower surface 142 (e.g., disposed away from trace 108). Openings 122,124, and 126 are formed in or completely through conductive layer 104.Openings 122, 124, and/or 126 may be filled with material from insulatorlayer 106 and/or from insulator layer 102.

Trace 108 is shown disposed above or over openings 122, 124, and 126 ofpath of openings 120. In some embodiments, layer 108 may be described asa microstrip trace. Opening 122 is shown having a length L1 and widthW1. Also, trace 108 is shown having width W2 and length equal to L2+L3.Width W2 may be a width as known for a signal trace or line, and/or thelike. Similarly, length L2+L3 may be a length known for a signal traceor line, and/or the like. Width W1 may be less than equal to or greaterthan width W2. Also, length L1 may be a length greater than less than,or equal to width W1. Length L1 and width W1 represent the footprintshape of openings 122, 124, and 126. Thus, those openings have a squarefootprint shape. However, it can be appreciated that other shapes areconsidered (e.g., see FIG. 3 and descriptions herein for FIG. 2B). Itcan also be appreciated that openings in addition to 122, 124, and 126may be formed along length L1 and/or L3 of trace 108. Similarly, it canbe appreciated that trace 108 may have a length, shape, and/or layoutdifferent than that shown in FIG. 1A. Thus, forming openings 122, 124,and 126 may change a ground parasitic of trace 108, thus changing oradjusting a signal phase velocity or a flying time of a signaltransmission along length L2+L3 of trace 108. Similarly, openings 122,124, and 126 may change a capacitive and/or inductive phasecharacteristic of trace 108. Thus, the openings may change or adjust atransmission skew of trace 108 as compared to another trace where trace108 and the other trace are a differential signal pair, such as toeffect a timing compensation of the differential signal pair of tracesor lines.

Layer 104 may represent a ground layer of a PCB or electronic device.Similarly, trace 108 may represent a trace or differential signal traceof fine of a PCB or electronic device. Layer 106 may represent adielectric material between trace 108 and layer 104, and layer 102 mayrepresent a dielectric or insulator layer disposed on the opposite sideof layer 104 from trace 108 of a PCB or electronic device. Layers 106and 102 may or may not be the same material. Trace 108 and layer 104 mayor may not be the same material.

As described herein, a signal or a trace may describe a high-speedsignal or a trace for transmitting a high speed signal. Similarly, a“trace” as described herein may include a single trace that is not atrace of a differential signal pair, a trace of a differential signalpair (e.g., a trace to transmit a signal where the other trace of thepair transmits a signal having an opposite phase with respect to time),or a like trace. Similarly, an electronic device as described herein mayinclude a semiconductor device, an electronic device formed on asubstrate, a transistor, a printed circuit board (PCB), a package (e.g.,for mounting or packaging a semiconductor device or other electronicdevice), or another electronic device, which may include a trace ordifferential signal traces or lines. Also, although descriptions hereinpertain to a PCB, the concepts described herein are also applicable totraces or lines of other electronic devices.

Layer or trace 108 is shown having thickness T1, layer 106 havingthickness T2, layer 104 having thickness T3, and layer 102 havingthickness T4. Thickness T1 may be a thickness appropriate for a trace orsignal line, or the like. Similarly, thickness T2 may be a thicknessappropriate or selected for an insulator or dielectric layer between atrace and a ground plane layer. Also, thickness T3 may be a thicknessappropriate for a ground plane layer. Similarly, thickness T4 may be athickness appropriate for an insulator layer formed below or under aground plane layer with respect to a trace (e.g., trace 108).Specifically, these thicknesses may be appropriate for the appropriatetrace or layer of a PCB, chip package, or electronic device, and/or thelike.

Thickness T1 may be a thickness of 0.1, 0.2, 0.4, 0.8, 1.0, 1.3, 2.0,4.0, 8.0, any combination thereof, or any range between any thickness orcombination thereof of mils in thickness (e.g., 1 mil equals 0.001inches). Thickness T3 may be a thickness similar to that described abovefor thickness T1. It is also appreciated that thickness T1 may be athickness of a trace or line for transmitting a signal on or in a PCB orelectronic device, as known in the art. Likewise, thickness T3 may be anappropriate thickness for a ground plane or conductive layer of a PCB orelectronic device, as known in the art.

Thickness T2 may be a thickness of at least 0.25, 0.5, 1, 2, 4, 5, 6, 8,10, 20, any combination thereof, or any range between any thickness orcombination thereof of mils. Thickness T4 may be a thickness equal to orgreater than that of thickness T2. It is also considered that thicknessT2 may be a thickness as known in the art for an insulator or dielectriclayer between a trace or line and a conductive ground layer of a PCB orelectronic device, as known in the art. Likewise, thickness T4 may be athickness of an insulator or dielectric layer on the opposite side of aground plane from a trace, as known in the art. In some cases, thicknessT4 will be a thickness similar to thickness T2, or may be a thickness ofan insulator or dielectric layer between a ground plane and a trace,such as in a case where a trace exists disposed on, touching, or awayfrom the surface of layer 102 opposite to that of surface 130. Forexample, openings 132, 134, and 136 may change a ground parasitic oftrace 108, as well as changing a ground parasitic of a trace formedtouching, on, or under the surface of layer 102 away from or opposed tosurface 130.

Distance D1 represents a distance or length between edges or side wallsof adjacent openings (e.g., between the sidewall of opening 122 closestto opening 124, and the sidewall of opening 124 closest to opening 122).Distance D1 may be a distance of 1, 2, 4, 5, 8, 10, any combinationthereof, or any range between any distance or combination thereof ofmil's (e.g., 1 mil equals 0.001 inches).

L1 may be a length of 1, 2, 4, 5, 8, 10, and/or a combination thereof ofmil's. W1 may be a distance as described above with respect to L1.Likewise, W2 may be a distance as described above with respect to L1. Itis also appreciated that W2 may be less than or greater than a distancedescribed above for L1. L2 and/or L3 may be 10×, 20×, 40×, 80×, 100×,200×, 400×, 800×, 1,000×, 2,000×, any combination thereof, or any rangebetween any multiple or combination thereof of multiples greater inlength than the distance described above for L1.

For example, in one embodiment, L1 may be 5 mils, W1 may be 4 mils, D1may be 5 mils, and W2 may be 5 mils, and L2 may be one inch. Also, inembodiments, thickness T1 and T3 may be 1.3 mils, and thickness T2 (anoptionally T4) may be 6 mils. Specifically, there may be approximatelyfifty openings along L2. In such an embodiment, it is possible that theflying time of a signal along the trace, or a skew for a differentialpair may be adjusted by between 2 and 5 pico-seconds. Approximately 50openings may describe 50+/−5 openings. Moreover, in the example above, anumber of openings greater than fifty may be used over a length greaterthan one inch, such as to reduce a phase velocity or skew by between 10pico-seconds and 100 pico-seconds.

Specifically, where phase velocity (V_(p))=1/(LC)^(1/2), the openings inthe ground layer may substantially increase L (e.g., by at least anamount of 1×, 2×, 4×, 8×, 10×, any combination thereof, or any rangebetween any multiple or combination thereof), and may causesubstantially no reduction in C (e.g., by reducing by no more than 10%,20%, 40%, 80%, any combination thereof, or any range between any percentor combination thereof). Thus, although C is decreased, it is decreasedby very little as compared to the increase in L (e.g., L is increased byan amount at least 2×, 3×, 4×, 8×, 10×, any combination thereof, or anyrange between any multiple or combination thereof of multiples greaterthan the decrease in C). As a result, V_(p) is reduced by the existenceof the openings (e.g., whether or not the openings are filled withinsulator material).

As a ground plane, layer 104 may provide a “ground” (GND), reference,and/or “0” voltage reference for the signal trace (e.g., trace 108).Layer 104 may be a ground plane layer of a PCB or electronic devicehaving a length and width or footprint (e.g., an area observed from atop perspective view, such as that shown in FIG. 1A and defined by L4multiplied by W4) that is much larger than that of the area or footprintof the trace for which the openings formed in the ground plane are underor adjacent to (e.g., trace 108). For example, L4×W4 of layer 104 may be3×, 4×, 5×, 6×, 10×, 20×, 40×, 80×, 100×, 200×, 400×, 500×, 800×, anycombination thereof, or any range between any multiple or combinationthereof of multiples greater than the surface area of trace 108 (e.g.,approximately W2×(L2-L3)). Specifically, the surface area and thicknessof area 104 is chosen, as known in the art, to be sufficient, to providea ground plane layer for trace 108 and any other traces formed on orwithin the PCB or electronic device which trace 108 and ground layer 104are a part of (e.g., such as a PCB or electronic device in which trace108 is a trace or line of a differential signal pair, and multiple othertraces and/or differential signal pair exist on or within the PCB orelectronic device, such as striplines and/or micro striplines).

FIG. 2A is a schematic cross-section view of a portion of an electronicdevice having a conductive layer on an insulator layer. FIG. 2A mayrepresent part of a device and/or process for forming the device of FIG.1A, 1B and/or 2G. FIG. 2A shows conductive layer 204 formed on insulatorlayer 102. Insulator layer 102 may be a dielectric (e.g., having variousdielectric constant values), a substrate, or another nonconductivelayer. Similarly, layer 102 may be a layer that is neither a conductornor a semiconductor, but is instead formed of an insulating materialand/or dielectric material.

In some cases, layer 102 may be a polymer, natural material, organicmaterial, synthetic material, non-synthetic material, or other insulatormaterial known of a PCB or electronic device. Also, layer 102 may be adielectric known in the art of forming semiconductor devices, such assilicon dioxide (SiO₂), silicon nitride (SiN₃) or the like. Layer 102may be formed by growing or deposition, such as by chemical vapordeposition (CVD), tetraethyl orthosilicate (TEOS) or a similar process.Layer 102 may have a dielectric constant that is less than thedielectric constant on silicon dioxide (e.g., a “low k” material),including polymers as known in the art.

Also, conductive layer 204 may be a layer of conductor material, such ascopper (Cu), gold, silver, lead, nickel, cobalt, titanium, tungsten,tantalum, a metal, an oxide thereof, a nitride thereof, and/or an alloythereof. Layer 204 may be formed by growing (e.g., such as on a seedlayer) deposition (e.g., CVD, PVD, ion implantation, and the like), orcoating (e.g., electron beam evaporation, crystal growth, sputtering,electrochemical coating, electroplating, physical deposition, and thelike. For instance, conductive layer 204 may be formed of a conductivematerial such as a metal, alloy, or other non-insulator,non-semiconductor material.

Layer 204 may be formed on, touching, and/or in direct contact withlayer 102. Alternatively, layer 204 may be formed over layer 204 such aswhere there are one or more layers between layer 102 and layer 204.Similar definitions may apply to other layers formed on, touching,physically contacting, over, above, other layers as described herein.Specifically, FIG. 2A also shows surface 130, such as a surface ofinsulator material 102. Surface 130 may be in direct contact or touchinga surface of conductive layer 204 (e.g., layer 204 is formed on surface130 of layer 102), or a layer of adhesive material may be formed betweenlayer 204 and surface 130 of layer 102.

Layer 204 may be formed by plating, such as electrolytic plating of ametal or metal alloy, or by electroless plating of an electrolessmaterial onto, on, over, above, overlying, and/or touching layer 102(e.g., surface 130). Also, it is considered that layer 204 may be formedof a material including one or more of a metal, a copper, a copperalloy, an aluminum, a nickel, a gold, a silver, a platinum, or apalladium material. It is also contemplated that the material of layer204 may be doped (e.g., such as with catalytic metals), annealed, orradiated with some form of energy to form an alloy. A tin, in indium, acadmium, a zinc, an aluminum, a bismuth, a ruthenium, a rhodium, arhenium, a cobalt, or a palladium material. Copper has become a popularchoice for conductive layers, such as ground plane layers for variousreasons, including to provide low resisitivity, such as a resisitivitythat is lower than that of aluminum or aluminum alloys.

Specifically, layer 204 of a material, such as copper, may be introducedby electroplating or physical deposition in a sufficient amount to formthickness T3 of material. In one instance, layer 204 may be formed byelectrolytic plating including the deposition of a material (e.g., ametal such as copper) using an external source of electric current.Here, an anode, made form a conductor (e.g., a metal such as copper),serves as a source of conductor (e.g., metal) ions, where the anode isunder a different potential voltage than a cathode (e.g., an electrolesscopper formed over surface 130 during a pre-treatment process, as knownin the art). Thus, conductor (e.g., a metal such as copper) on or aspart of the anode dissolves from the anode into conductor ions andmigrates to the cathode, and becomes deposited on surface 130 (e.g.,becomes deposited on the pretreated surface) to form a productiveconductive layer (e.g., to form layer 204).

In some cases, an electroplating process for forming layer 204 mayinvolve introducing layer 102 (e.g., a substrate, board, PCB, and/orelectronic device including layer 102) into an aquis solution containingmetal ions, such as copper sulfate, based solution, and reducing theions (reducing the oxidation number to a metallic state by applyingcurrent between layer 102 and an anode of an electroplating cell in thepresence of the solution). Alternatively, layer 204 may be formed by anelectroless plating process to form an electroless material layer of anelectrically conductive material. Such a process may include thedeposition of a conductive material (e.g., a metal such as copper) on acatalytic surface (e.g., such as palladium formed on surface 130) fromsolution without an external source of current. In some cases, a processfor forming electroless material as layer 204 may involve otherprocesses as know in the art.

Moreover, layers 204 and 102 may be assembled together, such as using alaser, heat, pressure, adhesion, stick, and/or “prepreg” process, and/orthe like. Specifically, a surface of layer 102 and/or 204 may be treatedor have a chemical property such that the layers adhere or attach toeach other upon contact or upon additional processing (e.g., pressing,heat treating and/or annealing). Moreover, adhering may include anadhesion layer of material between the two layers being assembled, suchas an adhesion material of epoxy, “glue”, “prepreg”, and/or the like. Insome case, layers may be laminated (glued with heat, pressure &sometimes vacuum) together. Thus, descriptions herein of forming layersand/or material on, touching, in direct contact with, above, or overother layers and/or material may include such adhesion processes and/ormaterials. Subsequently, portions, borders, edges, and/or openingthrough layer 204 may be etched by one or more standard metal etchprocesses, laser processes, and/or a drilling processes.

A PCB may have a physical composition including between one and sixteenor more conductive layers separated and supported by layers ofinsulating material (substrates) laminated (glued with heat, pressure &sometimes vacuum) together. A layer or substrate of PCBs may be made ofor include paper impregnated with phenolic resin, such as a compositematerial made of paper impregnated with a plasticized phenolformaldehyde resin. A substrate or layer may be or include a wovenfiberglass mat impregnated with a flame resistant epoxy resin. Alsoconsidered are layers and substrates for high power radio frequency (RF)work, which may include or be plastics with low dielectric constant(permittivity) and dissipation factor, such as polyimide, polystyreneand cross-linked polystyrene.

In some cases the layers or PCB may or may not have a conductive core,rigid core materials, flexible core materials (e.g. polyimide film),ceramic and/or metal cores. Usually an electronics engineer designs thecircuit, and a layout specialist designs the PCB. The designer must obeynumerous PCB layout guidelines to design a PCB that functions correctly,yet is inexpensive to manufacture. The standards organizations publishesdesign rules intended to ensure manufacturability of PCBs.

FIG. 2B shows the device of FIG. 2A after forming openings in theconductive layer. FIG. 2B shows conductive layer 104 having openings122, 124, and 126 to layer 102. For example, opening 122 may extendthrough layer 104 to surface 130 at portion 132 of the surface.Likewise, opening 124 may extend through layer 104 to portion 134 ofsurface 130; and opening 126 may extend through layer 104 to portion 136of surface 130 of layer 102. Hence, insulator material of layer 102 isexposed through holes 122, 124, and 126 at portion 132, 134, and 136 ofsurface 130.

Openings 122, 124, and/or 126 may have a footprint, profile, orotherwise define a shape with respect to a top perspective view ofsurface 140 of layer 104. For example, a footprint shape of one or moreof those openings may define a circle, a square, a triangle, arectangle, a polygon, a quadrilateral, an oval, or a combination thereofof shapes in surface 140. The footprint shape may extend through layer140 to define a similar shape at surface 130. Alternatively, the shapeand surface 140 may “fade” or otherwise define a different shape atsurface 130 (e.g., such as where etching to form the opening isperformed by isotropic an isotropic etching). Specifically, thefootprint shape in surface 140 may extend through layer 104 to anopposing surface of layer 104 to expose a similar shape at surface 130of layer 102.

For instance, openings 122, 124, and 126 may be formed by a processknown in the art for forming openings in a material described for layer204 and/or a material formed as described for layer 204. For example, incases where layer 204 is a conductive ground layer of a PCB orelectronic device, openings 122, 124, 126, and the like may be formedunder or adjacent to a trace by etching to form those openings throughlayer 204 during the same process or set of processes used to etch awayother portions of layer 204, such as to form borders around the groundplane, divide the ground plane into portions, or otherwise etch layer204. It can be appreciated that this allows etching to form the openingsto be “free” with respect to processing, such as by allowing theopenings to be formed without requiring any additional processing orsets of processes, other than those required already for etching layer104 to form the PCB or electronic device.

Openings 122, 124, and/or 126 may be formed by drilling, etching, othermechanic processes, other chemical processes, processes known forforming openings in the art of PCB, semiconductor chip, or otherelectronic device arts. In some cases, the openings may be formed byreactive ion etching (RIE), wet etching (e.g., using a liquid), dryetching (e.g., using one or more gases), or other processes sufficientto form an opening through layer 104. In some cases, the openings may beformed according to known techniques for forming openings in or removingportions of a trace, or conductive layer (e.g., a ground conductivelayer) as known in the art of PCB, semiconductor device, and/orelectronic device formation. Forming the openings may include, forexample, initially using a mask, such as a photoresist mask to definethe openings (e.g., the footprint shape), and etching layer 104 with asuitable chemistry. For example, non-plasma etch chemistries may includechlorine (Cl₂), hydrochloric acid (HCl), fluorine (F₂), bromine (Br₂),HBr and/or others. Plasma etches including chemistries of SF₆, NF₃ orthe like. The mask may then be removed (such as by oxygen plasma toremove photoresist). It is contemplated that various masks and/orprocesses may be used to form the openings.

Forming of the openings may be described as removing a portion of layer104 to form a hole, shaft, or other footprint shaped opening at leastthrough a portion of thickness T3 of layer 104. Also, it can beappreciated that more or fewer openings than three (e.g., 122, 124, and126) may be formed in layer 104 (e.g., under trace 108). Also, accordingto embodiments, layer 102 may be excluded or not exist below layer 104,such as where layer 104 is exposed and material that may be in openings122, 124, and 126 may or may not extend beyond the bottom of layer 104.

FIG. 2C shows the device of FIG. 2B after forming an insulator materialon the conductive layer and through the openings. FIG. 2C showsinsulator material 106 formed on conductive layer 104 and in openings122, 124, and 126. It can be appreciated that layer 104 may representlayer 204 after forming openings 122, 124, and 126 through layer 204.For example, insulator material 106 may be a layer of insulator materialformed on layer 104, and formed through openings 122, 124, 126, and tosurface 130 at portion 132, 134, and 136, respectively. Thus, material106 may touch or be in direct contact with layer 102 at portion 132,134, and 136. Alternatively, in some embodiments, material 106 may notbe in contact with layer 102 at any or all of portions 132, 134, and136. For example, material 106 may not extend into openings 122, 124, or126. Also, material 106 may extend only through a portion of thicknessT3 of layer 104, such that it does not contact surface 130 through someor all of the openings. Material 106 may be formed by one or moreprocesses similar to those described above with respect to forming layer102. Similarly, material 106 may be a material or layer of material asdescribed above with respect to layer 102. The material of insulatormaterial 106 within or through the openings may be described as a plug,column, cylinder, and/or filling of material in the opening. Similar tothe description of adhering layer 104 to layer 102, layer 106 may beadhered to layer 104. Thus, the material in the openings may be theadhesive material, stick, glue, epoxy, insulator, dielectric material,or prepreg material, and/or the like.

FIG. 2D shows the device of FIG. 2C after forming a conductive materialon the insulator material. FIG. 2D shows conductive layer 208 formed on,over or touching layer 106. Layer 208 may be formed of a conductormaterial and/or by a process as described with respect to forming layer104 on layer 102. Moreover, layer 208 may be adhered to layer 106 asdescribed with respect to adhering layer 104 to layer 102. Layer 208 maybe formed of a material known for forming signal traces or lines.

FIG. 2E shows the device of FIG. 2D after removing portions of theconductor material to form a signal trace. FIG. 2F shows a sideperspective view of FIG. 2D. Trace 108 is shown formed on, over ortouching layer 106. For example, layer 108 may be formed by removingportions of layer 208 as described above with respect to removingportions of layer 104. However, the portion of layer 108 left remainingmay define a signal trace, differential signal trace, pair ofdifferential signal traces, signal line, or trace as known in the art.Moreover, trace 108 may be disposed above, over, and/or adjacent toopenings 122, 124, and/or 126. Openings 122, 124, and/or 126, such as apath of openings 120, are each shown under, below, or adjacent to trace108. Similarly, one or more of the openings may be described as beingunder, below, or adjacent to trace 108. It can be appreciated that theterms, above, over, under, and/or below are relative and may be switcheddepending on the orientation or perspective with respect to layer 108and layer 104. Specifically, portions of layer 108 may be removed toform a trace adjacent, above, or over a path of openings, where the pathof openings is defined by openings 122, 124, and 126. It can beappreciated that other openings can be in the path, as long as they arebelow, under, or adjacent to trace 108. Also, portions of layer 208 maybe removed by known techniques by, for example, initially using a mask,such as a photoresist mask to define an area (e.g., a cross-sectionalarea defining a trace or signal transmission line) for removing portionsof layer 208 such that a trace or transmission line is left remainingafter etching with a suitable chemistry, such as described for etchinglayer 104. Thus, it can be appreciated, that layer 108 is layer 208after removing portions of layer 208.

FIG. 2G shows FIG. 2E after forming additional layers on the trace ofFIG. 2E. In some cases, after forming additional layers on trace 108(e.g., as shown in FIG. 2E) trace 108 may be described as a striplinetrace. FIG. 2G shows the structure of FIG. 2E including another groundplane layer having openings on or adjacent to trace 108 and anadditional trace on the lower surface of layer 102. Specifically, FIG.2G shows an embodiment where trace 108 is within or between insulatorlayers (e.g., such as being a stripline) of a PCB or electronic device.Likewise, trace 198 may be a trace formed on surface 142 of layer 102where portions of layer 142 are exposed (e.g., portions that are notcovered with traces such as trace 198 may be covered with a protectivematerial, but layer 142 is not and inner, mid, or other layer within thePCB or circuit device (e.g., is not a layer such as layer 106). Thus,layer 198 may be a micro strip on the surface of a PCB or electronicdevice. Trace 198 may have physical dimensions, be formed of a material,and/or be formed by processes similar to those described above withrespect to layer 108. The effect of openings 122, 124, and 126 on trace192 may be similar to those described with respect to the effect ofthose openings on trace 108.

FIG. 2G shows insulator or dielectric layer 176 formed on, above, ortouching trace 108 and layer 106. Similarly, conductive layer 174 isshown formed on, touching, or above layer 176, and insulator layer 172is shown formed on, above, or touching layer 174. Layers 176, 174, and172 may be formed of a material and/or by a process similar to thatdescribed with respect to forming layers 106, 104, and 102 respectively.Moreover, layer 174 is shown having openings 182, 184, and 186 throughlayer 174. Openings 182, 184, and 186 may correspond with descriptionsfor openings 122, 124, and 126, respectively. Specifically, lengths,widths, distances, and thicknesses of layer 176, layer 174, layer 172,opening 182, opening 184, and/or opening 186 may correspond with thosedescribed with respect to layer 106, layer 104, layer 102, opening 122,opening 124, and/or opening 126, respectively. For example, thicknessT5, T6, and/or T7 may correspond to thickness T2, T3, and T4 of FIG. 1B.Likewise, distance D2 may correspond to distance D1 of FIG. 1B.

It can also be appreciated that the process for forming openings 182,184, and 186 and/or filling those openings with insulating material maybe similar to that described with respect to openings 122, 124, and 126.Thus, it can be appreciated that the effect for change in the groundparasitic, signal phase velocity, flying time of a signal for trace 108caused by openings 182, 184, and 186 (with or without dielectricmaterial disposed therein) may be similar to the effect described withrespect to openings 122, 124, and 126. Specifically, openings 182, 184,and 186 may be above, over, or adjacent to trace 108 (e.g., with respectto a top perspective view. For instance, the geometry, material,formation of, material in, and/or spacing of openings 182, 184, and 186may be similar to descriptions with respect to openings 122, 124, and126 (e.g., see FIG. 1A), such as to double the change in groundparasitic and/or signal phase velocity for trace 108.

It is also noted that in addition to thickness T5, layer 176 includes athickness equal to thickness T1 of layer 108 such that layer 176 touchesor is in contact with layer 106. Moreover, similar to the descriptionabove for forming layers 102, 104, and 106, layer 176 may be formed on,touching, over, and/or adhered to trace 108 and the surface of layer106. Similarly, layer 174 may be formed on, touching, over, or adheredto layer 176 and/or layer 172. Finally layer 172, and/or layer 176 maybe formed on, touching, or adhered to layer 174, such as where materialof layer 172, and/or layer 176 may be formed though openings 182, 184,and 186 so that material of layer 172 contacts material of layer 176through the openings. Alternatively, the material of layer 172 may notcontact the material of layer 176 through the openings. Thus, in somecases, the material of layer 176 is formed on layer 174 and throughopenings 182, 184, and 186 to (e.g., touching) surface 180 or material172 similar to the descriptions with respect to forming material 106through openings 122, 124, and 126 to and touching surface 130 of layer102.

FIG. 2G shows trace 198 having thickness T8, such as a thicknessdescribed above with respect to thickness T1 and/or a thickness of amicro stripline as known in the art. In some cases, thickness T2 may be,thickness T4, and/or thickness T2+T1+T5 may be a thickness of between 2and 20 mil, of 3× the thickness of T1 (e.g., 2.53, or 3.5× the thicknessof a stripline as known in the art), and/or 5× the thickness ofthickness T8 (e.g., 4, 4.5, 5, 5.5, or 6 times the thickness of a microstripline, as known in the art). Thus, in some embodiments, thickness T4may be approximately 5× thickness T8, and/or thickness T2 may be equalto or approximately equal to 3× thickness T1.

Also, in some cases, trace 198 may have a width (e.g., a top perspectivewidth which would be a width such as shown by width W2 of trace 108, butfor trace 198) similar to that described above with respect to width W2.Also, trace 198 may have a width between 3 and 10 mil. It is alsoconsidered that trace 198 may have thickness T8 equal to between 1.3 and2.6 mil, equal to between 1 and 2 mil, and/or equal 1.9 mil. In somecases, the width and thickness of trace 198 (e.g., including thosedescribed above) may be that for embodiments where trace 198 is a microstrip. Moreover, trace 198 may have a width, length, thickness,material, and/or formed by a process as known in the art for forming amicro strip.

Likewise, trace 108 may be of a length, width, thickness, material,and/or formed by a process as known in the art for forming a stripline.In some cases, trace 108 will have width W2 similar to that describedfor a width of trace 198. Also, in some cases, trace 108 may have athickness as described for thickness T8. Also, trace 198 and/or trace108, and/or the other trace of a differential pair where trace 198and/or 108 is one trace of the pair, may have a length of between 0.1inches and 40 inches. For example, a trace or line as described hereinmay have a length of 0.1, 0.2, 0.4, 0.8, 1, 2, 4, 8, 10, 20, 40, anycombination thereof, or any range between any length or combinationthereof of inches in length.

FIG. 3 is a top perspective view of a differential pair of signal traceson a dielectric layer showing openings are formed through a ground planeof one trace. Any of the openings shown and described for FIG. 3 may beused as an opening or hole as described herein. FIG. 3 showsdifferential signal pair 300 including trace 308 and 318 formed on,above, or touching insulator layer 306. Specifically, trace 308 andtrace 318 may each be one of the traces or lines of a differentialsignal pair of traces or lines. Layer 306 may be an insulating layerformed on conductive layer 304 (e.g., a ground plane), which is in turnformed on layer 302. Layer 304 is shown having openings 322, 324, 326,328, 330, 332, 334, 336, and 338 which may correspond to opening 122 inlength, thickness, depth, width, formation of process, and/or materialdisposed therein or there through, with the exception of the length andwidth of those openings. In addition, the length, width, thickness,material, and process of layers 308, 306, 304, and 302 may correspond tothat described above with respect to layer 108, 106, 104, and 102,respectively. Also, the length, width, thickness, material and processof forming trace 318 may correspond to that for forming 108.Alternatively, the above noted geometry, material and processes forforming trace 308 and/or 318 may correspond to that of trace 186 (e.g.,such as where pair 300 are micro strips.

FIG. 3 also shows surface 310 of layer 306 between trace 308 and 318.Surface 310 includes midpoint line MP and distance D3 between trace 308and 318 where MP represent a midpoint of distance D3 between the inneredges or edges of trace 308 and 318 disposed towards each other. Trace308 is shown having width W2 and opening 336 is shown having length L1and width W1, such as where trace 308 and opening 336 correspond totrace 108 and opening 122 of FIG. 1A, respectively. However, the othertraces are shown having various other lengths and widths with respect towidth W2. The width of an opening may be centered with respect to acenterline CP of trace 308 (e.g., see opening 322) or may be offset withrespect to line CP (e.g., see opening 328).

Also, the spacing between the openings may be the same or different. Forexample, FIG. 3 shows opening 322 centered at a midpoint between opening324 and opening 328. However, opening 330 is not at a midpoint betweenopening 328 and opening 332, but is centered at a point closer toopening 328 than to opening 332. It is considered that openings may beequally centered between other openings, centered closer to someopenings than others, or a combination thereof for a path of openings(e.g., such as path 120). It is also considered that openings havingvarious widths and lengths, or having the same width and length, may beused in a path. For example, path 350 includes various shaped, andcentered openings with respect to line CP and each other. Moreover, path350 includes openings having various widths with respect to width W2 oftrace 308. Thus, a path of openings may include openings having the samecenter point with respect to line CP, with respect to each other, havingthe same width with respect to each other, having the same length withrespect to each other, or having one, any, or all of these differentwith respect to each other. For example, a proportion of width to lengthfor an opening may be 1×1, 1×1.5, 1×2, 1×2.5, 1×3, 1×4, 2×2, 2×1, 3×3,3×2, 2×3, 4×4, 4×3, 3×4, 4×2, 2×4, and the like with respect to eachother. In addition, those dimensions may provide minimum or maximumopening areas, such as with respect to a top perspective view as shownin FIG. 3.

According to embodiments, an opening may extend beyond the edges or bewider than width W2 of trace 308, such as shown by openings 124, 128,133, 134, and 138. In some cases, the opening may extend to thecenterline MP, but not beyond that line, between the trace the openingis under or “adjacent to” and the other trace of the differential pair.Specifically, all of the traces shown in FIG. 2D-2G may be described asbeing “adjacent to” trace 308, as none of them extends beyond line MP inthe direction of trace 318 (e.g., none of them extends beyond trace 308more than one-half distance D3). In addition to being adjacent to trace308, opening 336, 326, 322, and 320 may be described as being completelyunder trace 308. Likewise, openings 324, 328, 332, 334, and 338 may bedescribed as having a portion of those openings under trace 308. It canbe appreciated that although openings 334 and 338 are shown extendingaway from trace 318 a distance greater than distance D3, they are stilladjacent to trace 308 and do not extend past line MP towards trace 318.Thus, those openings change the ground parasitic of trace 308 more thanthat of trace 318, thus changing the signal phase velocity, flying time,or harmonic signal time propagation of trace 308. Specifically, any ofthose traces may change the skew of pair 300 by slowing the transmissionof a signal along trace 308 as compared to the transmission of itsdifferential signal along trace 318. Thus, any or all of the openingsshown in FIG. 3 may compensate for the situation where trace 308 isshorter in length than trace 318, but otherwise made of a material andhas a width and thickness similar to that of trace 318 to reduce a skewdue to the difference in length by causing a first part of adifferential signal transmitted on trace 308 to travel slower ascompared to a second part of a differential signal transmitted on trace318.

Distance D3 may be a distance of 1, 2, 4, 8, 10, 20, 40, 80, anycombination thereof, or any range between any distance or combinationthereof of mils in distance. In some cases, distance D3 may be 3×thickness T4, T2, T1+T2, T1+T2+T5, or another thickness of a dielectriclayer of a printed circuit board or electronic device between a groundlayer and a trace or another ground layer of the PCB or device. In somecase, distance D3 may be a distance of between 6 and 18 mil. Finally,distance D3 may be a distance between traces, and/or differential linesof a PCB or electronic device.

It is also considered that the footprint size (e.g., length times width,surface area, or area shape from a top perspective view as shown in FIG.3) of one or more of the openings may be selected or designed tocompensate, reduce, or remove a skew and signal phase velocity (e.g., atiming compensation) due to a longer length of trace 318 as compared totrace 308. Also, each trace shown in FIG. 3 may be described as being“closer to” trace 308 then it is to trace 318 since none of the openingscross line MP. Although not shown, it is considered that someembodiments may include openings that actually extend across line MP,but that are closer to trace 308 by having most of their footprint areacloser to trace 308 than to trace 318 with respect to line MP. In fact,in some embodiments, no portion of an opening may be directly undertrace 308, however, a majority of the footprint of the opening may becloser to trace 308 than to trace 318. In some embodiments, openings maybe selected or designed to have a sufficient number of openings having asufficient footprint size to be formed through a conductive layer (e.g.,a ground plane) to slow transmission of a first portion of adifferential signal on a trace (e.g., trace 308) to substantiallyeliminate a skew. FIGS. 4A and/or 4B below, may or may not provide suchan embodiment.

FIG. 4A is a top perspective view of a pair of differential signals totransmit signals between two semiconductor chips. FIG. 4A showselectronic device 400 including two chips connected by traces or linesof differential signal pair 402. Specifically, pair 402 includes trace408 and trace 418. For example, pair 402 may connect electroniccircuitry of chip 1 and chip 2 by being a differential pair of microstrips or striplines to carry the two parts of a differential signalfrom chip 1 to and from chip 2. Electronic device 400 may represent aprinted circuit board having chip 1 and chip 2 mounted on that PCB. Pair402 may be electronically connected or attached to contacts, wires,traces, or other electrical connection points of chip 1 and chip 2, suchas known in the art. Also, FIG. 4B is an example of a schematiccross-section view through line B-B′ of FIG. 4A. FIG. 4B shows trace 418and 408 within insulator layer 406 and having conductive layers 404 and474 (e.g., ground planes or ground conductor planes) above and belowtraces 408 and 418.

Specifically, FIGS. 4A and 4B will now be described with respect toembodiments where traces 408 and 418 are striplines, layer 406 is adielectric layer, and layers 404 and 474 are ground plane layers havingcorresponding openings 422 a and 422 b (openings 422 a and 422 brepresenting opening 422 of FIG. 4A) below and above trace 408,respectively. The length of trace 408 is shorter than that of trace 418.Thus, in order to slow down a part of a differential signal transmittedon trace 408, trace 408 includes path of openings P1 and P2 eachincluding openings over, under, adjacent to, along, and/or closer totrace 408 than to trace 418. For example, opening 422, 424 . . . , 442,444, and 446 of path P1 are shown along length LP1. As shown in thebreak in the traces, openings and lengths of path P1 may includeadditional openings and/or lengths. The openings of path P1 may havesimilar and/or different lengths, widths, center points, footprints,etc., as described herein. Similarly, path P2 is shown includingopenings 452, 454 . . . , 472, 474, and 476; and having length LP2.Openings and lengths of path P2 may or may not correspond to those withrespect to path P1.

Thus, paths P1 and/or path P2 may correct for the difference in lengthbetween shorter trace 408 and longer trace 418 by slowing the signalphase velocity or flying time of a signal transmission on trace 408 withrespect to that of the signal phase velocity or flying time of a signaltransmitted on trace 418 to completely or substantially correct for theskew of a differential signal transmitted on trace 408 and 418 betweenchip 1 and chip 2. In some cases, path P1 and/or path P2 may includebetween 6 and 6,000 openings each, such as where a path includes 6, 7,8, 9, 10, 20, 40, 80, 100, 200, 400, 800, 1000, 2000, 4000, 6000, anycombination thereof, or any range between any number or combinationthereof of numbers of openings that may or may not be filed withinsulator material, as described herein.

According to embodiments, the length of trace 408 may be 30 mil shorterthen that of the trace 418 leading to a skew of about 5 pico-seconds(e.g., without the openings of path P1 and P2, the same signaltransmitted by chip 1 on traces 408 and 418 would arrive at chip 2 about5 pico-seconds earlier from path 408 then path 418). In order tocompensate for the skew, paths P1 and P2 may each have a length (LP1 andLP2) equal to 0.5 inches and have a number of openings (e.g., opening422 through 446, and 452 through 476) of 50 openings. Thus a totallength of one inch having 100 openings filled with insulator materialthrough those openings in a ground plane below traces 408 and 418 isprovided. Specifically, as shown in FIG. 4B, thicknesses T46, T45, T41,T42, and T43 may be 1.3 mil, 6 ml, 1.3 mil, 6 mil, and 1.3 mil,respectively. Moreover, widths W41 and W42 may be 4 mil and 5 mil,respectively; and distance D41 may be 5 ml. Thus, as shown in FIG. 4B,where opening 422 a and 422 b represent each of the 50 openings alongpath P1 and each of the additional 50 openings along path P2, a skewcompensation of 5 pico-seconds between traces 408 and 418 may becompensated for, such as without adding length to or otherwiseredesigning or relaying out trace 408, or trace 418 (e.g., withoutchanging the length or layout of either trace after an initial designbut instead by forming the openings in path P1 and P2 duringmanufacturing). The geometries and dimensions above are examples, asother geometries, dimensions, thicknesses, widths, lengths, numbers ofopenings, and the like are considered for compensating the skew (e.g.,to correct for the difference in length between the traces).

For example, traces 418 and 408 may represent D+ and D− signal traces,respectively, of a micro stripline differential pair. Holes on groundhave been cut adjacent to D− so that from transmission line point ofview, L and C will be different for D+ and D−. Therefore, signals of D+and D− will propagate at different phase velocities. So if there is skewor timing difference between D+ and D− originally (e.g., the differencedue to the length of trace 408 being shorter than trace 418), then afterpropagation through this transmission line section, the skew or timingdifference can be compensated. According to embodiments, there can bedifferent geometries or patterns for hole distribution on the groundplane(s) to achieve optimized performance in skew/timing compensation.

This same principle or concept also applies to stripline differentialpair. Specifically, if traces 408 and 418 are a stripline differentialpair, holes may be cut in the ground plane below trace 408 to compensatefor the skew (since there is not ground plane above the traces). It canbe appreciated that in such an example, the number of holes in thesingle plan will have to include all of the holes from both planes ofFIGS. 4A and 4B (e.g., 200 holes below or adjacent to trace 408 in plane404 provides the same compensation as described above for both planes ofFIGS. 4A and 4B).

The concepts described herein may be used to slow the signaltransmission speed or phase velocity of transmission along the shorterlength trace of a pair of differential signal traces or line, by formingopenings through a ground conductive layer below, above, or adjacent tothe shorter length trace. Specifically, those openings may be closer tothe shorter length trace then to the longer length trace, thus changingthe ground parasitic and reducing the signal transmission speed orvelocity for a signal along the shorter trace, such that the opposingphases or polarities of differential signals along the differentialsignal pair transmitted from a transmission or start location of thepair arrive at an end or receive location of the pair at the same time,or substantially at the same time. Substantially at the same time may bedefined as within 1, 2, 4, 8, 10, any combination thereof, or any rangebetween any number or combination thereof of pico-seconds. The conceptsherein may be used to adjust a skew of a differential pair that is equalto or greater than 10, 20, 40, 80, 100, 200, any combination thereof, orany range between any number or combination thereof of pico-seconds. Asknown, the magnitude of the skew is often proportional to the distanceor difference in distance of length of differential signal pairs.Concepts herein may be used to substantially eliminate such a skew byreducing it to within 1, 2, 4, 8, 10, any combination thereof, or anyrange between any number or combination thereof of pico-seconds.Concepts herein may be used to correct a skew to reduce or remove commonmode between the differential signal line pair, such as to the extentnecessary to allow a receiver to decode the signal (e.g., signals on thepair) received.

Accordingly, it is possible to change the phase velocity of a trace byforming openings in a ground plane adjacent to, disposed above, and/ordisposed below the trace and filling the openings with an insulator ordielectric to adjust a ground parasitic of the trace. Thus, the phasevelocity of a trace can be changed without adjusting the length, width,thickness, and/or material of the trace. Moreover, this also allowsadjusting a skew compensation of a differential signal pair withoutchanging the length, width, thickness, material, and/or routing ofeither of the traces of the differential pair. It can be appreciatedthat a benefit realized includes adjusting a phase velocity of a traceafter the design, selection, and/or testing of the phase velocity and/ora time to send a signal having one or more frequencies from one locationon the trace to another location on the trace without changing a layoutor routing of the trace (e.g., such as on a PCB or electronic device).In some cases, pairs of differential signal traces may be designed, suchas for a layout on or within a PCB or electronic device. Thetransmission of signals on the differential pairs may be tested on acomputer or on a prototype of the PCB or electronic device. Then,undesirable or skew of pairs of traces may be corrected without changingthe design or selection of the layout by forming openings in one or moreground conductive layers of the PCB or electronic device above and/orunder one or both of the traces of each differential pair. Thus, it ispossible to form or manufacture PCBs or electronic devices according tothe design or selection of layouts without redesigning or creating asecond layout of differential pairs having a skew adjusted by formingopenings in the ground conductive layers. Benefits of this capabilityare an easier, economical, and efficient way to adjust the skew ofdifferential signal pairs or of single traces (e.g., traces that are notdifferential signal pairs) without redesigning or selecting a differentlayout or routing of any of the traces of the PCB or electronic device.

The invention is not limited to the specific embodiments describedabove. For example, concepts described herein may be applicable to anysignal transmission line or medium where transmission speed is affectedby ground parasitic changes, a geometry of (e.g., openings in) a groundplane or grounded medium under, over or adjacent to the transmissionline or medium. Accordingly, other embodiments are within the scope ofthe claims.

1. A method of changing a ground parasitic of a trace of a differentialsignal pair of signal traces comprising: forming a plurality of openingsthrough a conductive ground layer of a printed circuit board (PCB) underthe trace, wherein forming changes a capacitive phase characteristic ofthe trace and changes an inductive phase characteristic of the trace. 2.The method of claim 1 wherein the plurality of openings are a pluralityof non-conductive openings through the conductive ground layer.
 3. Themethod of claim 1 wherein the trace is a differential trace of one of amicro strip pair and a stripline pair of a printed circuit board (PCB)or a semiconductor chip package.
 4. The method of claim 1 furthercomprising forming a plurality of columns of insulator material in theopenings, wherein the columns have a square footprint shape defined on atop surface of the ground layer.
 5. The method of claim 4 wherein thecolumns of insulator material are columns of only insulator material inthe openings.
 6. A method of adjusting a signal transmission skew of adifferential signal pair of signal traces comprising: forming aplurality of openings through a conductive ground layer of a printedcircuit board (PCB) under a first trace of the differential signal pair,wherein forming changes a capacitive phase characteristic of the firsttrace and changes an inductive phase characteristic of the first trace.7. The method of claim 6 wherein the characteristic is proportional to asquare root of a product of an inductance and a capacitance of the traceand the ground layer.
 8. The method of claim 6 further comprising:forming an insulator material layer on the conductive ground layer andthrough the openings; forming the trace on the insulating layer over theopenings.
 9. The method of claim 8 wherein the insulator materialextends to a surface of a second insulator layer below the ground layer.10. A printed circuit board (PCB) comprising: a layer of conductivematerial formed on a layer of insulator material; a first differentialtrace and a second differential trace formed on the insulator layer,wherein a first length of the first differential trace is a longerlength than a second length of the second differential trace; aplurality of openings in the conductive layer filled with the insulatormaterial, each opening disposed closer to the first trace than to thesecond trace and having at least a portion of the opening under thefirst trace.
 11. The PCB of claim 10 wherein a footprint size of theopenings compensates for a skew in signal phase velocity due to thelonger length of the first trace as compared to the second trace. 12.The PCB of claim 10 wherein the plurality of openings cause a first partof a differential signal transmitted on the first trace to travel sloweras compared to a second part of a differential signal transmitted on thesecond trace.
 13. The PCB of claim 10 wherein the first and second tracecomprise a pair of differential traces and the plurality of openingscomprise openings in the conductive layer under the first trace andfilled with the insulator material to correct a skew between the pair ofdifferential traces.
 14. The PCB of claim 10 wherein the first andsecond trace comprise a pair of differential traces and the plurality ofopenings: (1) change a capacitive phase characteristic and an inductivephase characteristic of the first trace, and (2) cause the a capacitivephase characteristic and an inductive phase characteristic of the firsttrace to be different than a capacitive phase characteristic and aninductive phase characteristic of the second trace.
 15. The PCB of claim10 wherein the openings comprise a sufficient number of openings havinga sufficient footprint size in the conductive layer to slow transmissionof the first portion of the differential signal on the first trace tosubstantially eliminate the skew.
 16. The PCB of claim 10 wherein thefirst conductive layer comprises a ground layer, and the insulator layercomprises a layer of printed circuit board (PCB) or dielectric material,and the insulator layer is disposed between the ground layer and thetraces.
 17. The PCB of claim 10 wherein the openings comprise afootprint shape in a surface of the conductor defined by one of acircle, a square, a triangle, a rectangle, a polygon, a polyhedron,extending through the first conductive layer to a second insulator layerdisposed on an opposing surface of the first conductive layer from theinsulator layer.